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The following procedure describes how the coprocessor of Lab 1 can be packaged as an IP which can be used in IP Integrator. A more tedious alternative will be to make the connections yourself using HDL in the wrapper.

There could be slight differences in what you see based on the version of Vivado, but the spirit of the instructions below remains the same.

We can continue from the hardware platform project from Lab 2 as shown below. You could also package the IP in a separate project rather than in Lab 2 project. The packaged IP can be imported into the project you want it in (e.g., the Lab 2 project). Either way, the steps for packaging is the same.

Let us assume you are starting with your Lab 2 project. The following screenshots do not have AXI BRAMs integrated, as they form just additional memory and are not essential. The GPIO peripheral(s) is not essential either. Nevertheless, it is included for the sake of having at least one peripheral. The exact block diagram will vary for you depending on the number (which could be 0 too) of GPIOs / BRAMs etc, but does not fundamentally change what you do in the lab.

Select Tool → Create and Package IP. The Create and Package IP dialog will appear. Click Next.

Select Create a New AXI4 Peripheral. Then Next, you may use the default settings. Next again.

Configure the S00_AXI interface as below.

Then click on the green “plus” icon to add new interface. Configure it as follows

Click Next. Select Add IP to the Repository then Finish.

Now we can add our custom IP to the design. Choose Add IP and search for myip. Do not make any connections to the added IP as yet.

We need to modify our custom IP. Right-click to the block, select Edit in IP Packager. Vivado will create another Vivado project to edit the IP just as the one you work within Lab 1. The default location will be inside your project folder, <project_name>.tmp folder.

The template design generated by Vivado is a bit complicated, you can use the template code provided in Lab 1 to replace the content of myip_v1_0.vhd/v. You should also add matrix_multiply.vhd/v and memory_RAM.vhd/v to the project by right-clicking Design Sources and choosing Add Sources. While adding the file, check the option 'Copy sources into IP directory' and uncheck 'Scan and add RTL include files into project' (this will keep the files in the IP directory, which is a good idea).

You may need to specify the new top module after saving the content. Choose myip_v1_0.

Remove the myip_v1_0_M00_AXIS.vhd/v and myip_v1_0_S00_AXIS.vhd/v from the project. (Right-click, select Remove File from Project)

Then we have to reconfigure the IP configurations to allow the original Vivado project to recognize the new IP interfaces correctly. Click the Package IP (or Edit Packaged IP) in the Flow Navigator.

In the IP File Groups, add matrix_multiply.vhd/v and memory_RAM.vhd/v and remove myip_v1_0_M00_AXIS.vhd/v and myip_v1_0_S00_AXIS.vhd/v from the Verilog/VHDL synthesis and Verilog/VHDL simulation groups. Newer versions of Vivado can do this automatically when you click Merge changes from File Groups Wizard

In the IP Customization Parameters, remove all the Parameters because they are old parameters created by Vivado after generating the custom IP.

In the IP Ports and Interfaces, click Merge Changes … 

Select the first three interfaces as below (you have to expand the Clock and Reset Signals group to select the signals inside) and Remove them as we are going to create the new ones. There should be a green tick next to Ports and Interfaces.

If you get errors / critical warnings, those signals inside Clock and Reset Signals might not have been removed. Make sure the 4 signals shown below are removed.

Then, select 4 AXIS slave signals, right-click, choose Auto Infer Interface.

Choose AXIS (AXI>axis_rtl in newer versions of Vivado) and click OK twice.

Do the same for the AXIS master signals.

Newer versions of VivadoOlder versions of Vivado

Right-click on the ACLK signal and set it as Clock as below.

Right-click on ACLK signal and choose Auto Infer Interface.

Select Signal>clock_rtl as below and OK.

Similarly, repeat the above step for the ARESETN, but select Rese(Signal>reset_rtl in new versions) instead of Clock.

If you see a warning against Addressing and Memory, right-click on S00_AXI and select Remove Memory Map. A memory map is required only for AXI/AXI Lite interfaces, which are connected to the AXI bus and are addressable by the processor. AXIS cannot be connected directly, does not involve 'addressing' and hence, there is no need for a memory map. If the warning "The memory map 'S00_AXI' is not referenced by any bus interface." persists even after removing the memory map, ignore it.

At this point, we have finished customizing our IP, select Review and Package, and click Re-package IP to save the changes.

If you have done this packaging in a standalone project, you have already completed the IP packaging. You can close the project and import this to the project you want this in following the steps given in Coprocessor Integration using AXI Stream FIFO.

If you did this inside the Lab 2 project, continue the steps below.

Newer versions of VivadoOlder versions of Vivado

Once you come back to your main Vivado project, it will show a banner as shown below, and clicking Report IP Status / Show IP Status will open up the IP Status Tab. Ensure myip_0 is selected, and click Upgrade Selected.

An IP Upgrade Completed will pop up. You will see the new custom IP block in the block design panel.

When you dismiss the message by clicking OK, it will show up a Generate Output Products window. 

Click Generate*. Once the output products are generated, click OK to dismiss the message.  The IP Status will again show that one or more IPs have changed. You might get errors such as "The following clock pins are not connected to a valid clock source", and that is ok because we have not made any connections yet. Click Rerun again if possible (to regenerate the reports, but you may not be able to since the generation won't be successful); you need not (and won't be able to) click Upgrade Selected this time.

*You could in fact Skip it as the generation won't be successful before you make connections. However, skipping can sometimes result in the block interfaces not getting updated properly in the block diagram.

Once you come back to your main Vivado project, it may show that some IPs have changed in the IP Status tab (which shows up only if the IP Integrator is selected from the Flow Navigator). Click Rerun, and then Upgrade Selected.

An IP Upgrade Completed will pop up. When you dismiss the message by clicking OK, it will show up a Generate Output Products window. Click Generate. Once the output products are generated, click OK to dismiss the message.  The IP Status will again show that one or more IPs have changed. Click Rerun again, but you need not (and won't be able to) click Upgrade Selected this time. 

Eventually, you will see a block as shown below in the IP Integrator.

You can now go to Coprocessor Integration using AXI Stream FIFO page and proceed with integrating this IP with the rest of your system.​

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  1. The template design generated by Vivado is a bit complicated, you can use the simpler code provided in lab3_coprocessor.vhd/v to replace the content of myip_v1_0.vhd/v.

    The lab3_coprocessor.vhd/v files seem to be missing. Is this intentional?

    1. Vestige from last semester (sad). Please read it as "you can use the template code provided in Lab 1 to replace"...

      1. Do I use lab3_coprocessor.v file found in the attachment or the template from lab 1?

        The diff between the 2 files is that lab3_coprocessor.v does not have the module link for A_RAM, B_RAM, and RES_RAM.

        When I use the template from lab 1, there is error about missing memory_RAM.v files during synthesis.

        1. We're supposed to use all 3 template files from lab 1. So after replacing the my ip with the lab 1 template, I added in the RAM and matrix multiply templates. 

          1. Indeed. If we don't add it to the temporary packager project, the tool won't be able to find matrix multiply and RAM modules and your HDL codes won't be complete enough for synthesis. You won't have to start over, just right-click the IP to Edit in IP Packager, add the 2 component files to the temporary project, and click the 'Merge changes from File Groups Wizard' in the File Groups tab. Then Review and Package > Re-Package IP, and Upgrade Selected in the original project.

            1. Now I think about it, it doesn't make sense not including them...
              Yeah. The problem is solved.
              Thanks for the help and clarification.

  2. Hi,

    I encountered a problem when generating output product.

    The error is preventing me from proceeding.

    1. Right now, you have completed packaged your IP. That is just one block with no connections, so the error you are getting is expected. You need the rest of the blocks for completing a system. Either you can import this IP into your Lab 2 project as mentioned in the Adding the IP section, or you can just add the relevant stuff (Zynq processing system, etc. as you did for Lab 2) in this project itself.

      I have made some edits to clarify this at the beginning of this page, as well as at the point where a standalone project can be quit, as the packaging is already done (which is the case for you).

  3. Hi Prof,

    When we receive the final result matrix from the co-processor, do we have to capture the results in a csv/text file or is the displaying the result matrix in real term good enough? Thanks!

    1. If you can display it, it's pretty easy to capture it to a file, right? :)

  4. Ok I already did that. Thanks prof!